Method of fabricating a MOS device having a gate-side air-gap st

Details Method of fabricating a MOS device having a gate-side air-gap st Method of fabricating a MOS device having a gate-side air-gap st

1997-05-21

1998-04-07

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438773, 438960, H01L 218234

Patent

active

057364460

ABSTRACT:
A method of fabricating a MOS device having a gate-side air-gap structure is provided. A nitride spacer for reserving space of the air gap is formed on the substrate adjacent to the gate structure. An amorphous silicon spacer for forming the sidewall spacer and sealing the air gap is formed adjacent to the nitride spacer. The upper portion of the amorphous silicon spacer is heavily doped during the source/drain implantation. After removing the nitride spacer the doped amorphous silicon spacer is oxidized by a wet oxidation process to form a doped oxide spacer. The growing doped oxide spacer will seal the hole for the nitride spacer resulting from the heavily doped upper portion having a higher oxidation rate than that of other portions. Dopants implanted in the amorphous silicon spacer migrate into the substrate and extended ultra-shallow doped regions are formed that reduce the series resistance of the LDD structure.

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"A Self-Aligned Counter Well-Doping Technology Utilizing Channeling Ion Implantation and Its Application to 0.25 .mu.m CMOS Process" H. Nakamura et al., Symp. on VLSI Tech. Dig., p. 67, 1995.

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