Semiconductor processing method of forming complementary NMOS an

Details Semiconductor processing method of forming complementary NMOS an Semiconductor processing method of forming complementary NMOS an

1995-11-27

1998-04-07

Dang, Trung

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438155, 438231, 438527, H01L 218238

Patent

active

057364400

ABSTRACT:
A semiconductor processing method of forming complementary NMOS and PMOS field effect transistors on a substrate comprises the following steps: (a) providing a first conductivity type region and a second conductivity type region of the semiconductor substrate, one of the first and second type regions being an n-type region and the other being a p-type region; (b) providing a first transistor gate over the first conductivity type region, the first transistor gate defining the gate of a second conductivity type field effect transistor; (c) providing a second transistor gate over the second conductivity type region, the second transistor gate defining the gate of a first conductivity type field effect transistor; (d) providing an implant masking layer over the first conductivity type region; and (e) ion implanting a second conductivity type dopant into the first conductivity type region through the implant masking layer to define graded junction regions for the second conductivity type field effect transistor and simultaneously ion implanting the second conductivity type dopant into the second conductivity type region to define halo implant regions for the first conductivity type field effect transistor. Field effect transistors produced in accordance with this invention are also disclosed.

REFERENCES:
patent: 5427964 (1995-06-01), Kaneshiro et al.
patent: 5441906 (1995-08-01), Burger
patent: 5500379 (1996-03-01), Odake et al.
patent: 5532176 (1996-07-01), Katada et al.

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