Register circuit used to load, hold, and dump digital logic sign

Details Register circuit used to load, hold, and dump digital logic sign Register circuit used to load, hold, and dump digital logic sign

1986-04-21

1987-10-27

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

G11C 700

Patent

active

047034572

ABSTRACT:
A register sub-circuit for a logic system is described which is capable of loading a logic signal from a bus, holding the state of the logic signal, and dumping the logic signal onto a precharged high capacitance bus. The circuit is master/slave in operation permitting the register to simultaneously dump the current contents of the register at the same time a new value is being loaded into the register. The circuit operates with a single phase clock. The circuit is easily integratable. The circuit comprises a storage sub-circuit and one or more dump sub-circuits. The circuit presents a low capacitance load to the dump control line.

REFERENCES:
patent: 4437171 (1984-03-01), Hudson et al.
patent: 4570244 (1986-02-01), Sud et al.

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