Semiconductor device and method for manufacturing same

Details Semiconductor device and method for manufacturing same Semiconductor device and method for manufacturing same

1998-02-20

2000-11-21

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438303, H01L 21336

Patent

active

061502219

ABSTRACT:
It is an object of the invention to provide a CMOS device comprising p-channel FETs having shallow source and drain regions and a method for fabricating the same. A B-doped selective epitaxial layer is grown only on an area, where the source and drain regions of the p-channel FET is to be formed. Growth of the B-doped selective epitaxial layer on an area, where the source and drain regions of a n-channel FET is to be formed, is impeded by forming a amorphous region on the area corresponding to the n-channel FET.

REFERENCES:
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patent: 5683920 (1997-11-01), Lee
patent: 5707896 (1998-01-01), Chiang et al.
patent: 5753548 (1998-05-01), Yu et al.
patent: 5955745 (1999-07-01), Yamazaki
Fair, Richard B., "The Role of Transient Damage Annealing in Shallow Junction Formation", Nuclear Instruments and Methods in Physics Research B37/38 (1989)371-378, North Holland, Amsterdam.

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