Process for fabrication of a dram cell having a stacked capacito

Details Process for fabrication of a dram cell having a stacked capacito Process for fabrication of a dram cell having a stacked capacito

1998-02-03

2000-08-29

Dutton, Brian

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438397, H01L 218242, H01L 2120

Patent

active

061107751

ABSTRACT:
A DRAM cell transistor formed on a silicon substrate comprises a first BPSG film, a silicon oxide film as a supporting film laid thereover, a storage node including a contact portion filling a contact hole extended through the silicon oxide film and the first BPSG film, an oxidized silicon nitride film as a capacitor insulating film, and a plate electrode. There may be further provided a second BPSG film thereover. Even if the first BPSG film at a lower level is caused to reflow by a process for oxidizing the silicon nitride film for formation of the oxidized silicon nitride film as the capacitor insulating film or a process for ref lowing the second BPSG film, the silicon oxide film as the supporting film applies to the capacitor insulating film a stress against the deformation thereof and hence, the oxidized silicon nitride film free from wrinkle or cracks is provided as the capacitor insulating film. Thus, a semiconductor device free from wrinkle or cracks in the nitride film associated with thermal history and a process for fabrication of the same can be offered, even though the nitride film is laid over the insulating film having a reflowable property.

REFERENCES:
patent: 5399518 (1995-03-01), Sim

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