Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1985-02-13
1987-12-15
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365230, 365203, 307446, G11C 800
Patent
active
047137967
ABSTRACT:
In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.
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patent: 4616146 (1986-10-01), Lee et al.
F. Lee et al, "Cool-Running 16K RAM Rivals N-Channel MOS Performance", Electronics, Oct. 6, 1981, pp. 120-123.
R. M. Pate et al, "PROM Needs Far Less Power Than Bipolar Counterparts", Electronics, Oct. 6, 1981, pp. 124-126.
K. Yu et al, "C-MOS Static RAM Feels at Home with ECL Speeds", Electronics, Feb. 10, 1982, pp. 160-163.
K. Schrack, "Schnelle CMOS-Logikbausteine", Elektronik, Apr. 22, 1983, pp. 49-52.
K. Schrack, "Schnelle CMOS-Logikbausteine", Elektronik, Jun. 16, 1983, pp. 63-66.
V. K. Goser, "Speicherkleiner Verlustleistung in P-Kanal MOS Technik mit Sonderprozessen und in Komplementarkanal MOS Technik", NTZ 1973, H. 1, pp. 9-15.
P. P. Castrucci et al., "Bipolar/FET High-Performance Circuit", IBM Tech. Disclosure Bull., vol. 16, No. 8, Jan. 1974, pp. 2719-2720.
Masuda Ikuro
Odaka Masanori
Ogiue Katsumi
Suzuki Yukio
Uchida Hideaki
Hitachi , Ltd.
Popek Joseph A.
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