Method of forming stacked and trench type DRAM capacitor

Details Method of forming stacked and trench type DRAM capacitor Method of forming stacked and trench type DRAM capacitor

1998-04-21

1999-11-23

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, 438396, 438397, H01L 218242

Patent

active

059899557

ABSTRACT:
A DRAM capacitor structure and its manufacturing include covering a semiconductor substrate with a first conducting layer. A first insulating layer and a second insulating layer are alternately stacked at least once above the first conducting layer to form a multi-layered structure. A contact window opening is formed in the multi-layered structure to expose a source/drain region located above the semiconductor substrate. A pattern is etch-defined on the multi-layered structure, using the first insulating layer as an etching stop layer. Part of the second insulating layer is etched away to form a cross-sectional profile similar to twin towers, with each tower having the form of a vertical T-stack. A second conducting layer covers the multi-layered structure. The first insulating layer and the second insulating layer of the multi-layered structure, as well as the second conducting layer in a top part of the multi-layered structure, are etched away to form a lower electrode. A dielectric layer is formed above the lower electrode. An upper electrode is formed above the dielectric layer.

REFERENCES:
patent: 5434812 (1995-07-01), Tseng
patent: 5637523 (1997-06-01), Fazan et al.
patent: 5688709 (1997-11-01), Rostoker
patent: 5891772 (1999-04-01), Hsu
patent: 5910667 (1999-06-01), Hsu

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