Method for forming source drain junction areas self-aligned betw

Details Method for forming source drain junction areas self-aligned betw Method for forming source drain junction areas self-aligned betw

1997-06-20

1999-03-30

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438155, 438305, 438588, H01L 21336

Patent

active

058888721

ABSTRACT:
An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed and isolated from another polysilicon structure lying in the same elevated plane. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A first transistor is provided which is disposed upon and within a silicon-based substrate. A primary interlevel dielectric is deposited across the transistor and the substrate. Polysilicon may then be deposited across the primary interlevel dielectric and doped using ion implantation. A second transistor may be formed upon and within a portion of the polysilicon layer. The second transistor has a pair of implant regions spaced from each other by a gate conductor and a pair of oxide spacers arranged on opposed sidewall surfaces of the gate conductor. Part of the polysilicon layer is removed such that polysilicon only extends under the gate conductor and terminates a pre-defined distance from each of the pair of oxide spacers. A pair of junctions remain for the second transistor that are defined between an etched lateral edge and an oxide spacer. A second interlevel dielectric may be deposited across the second transistor and exposed areas of the primary interlevel dielectric to isolate the transistor from other active devices.

REFERENCES:
patent: 4381201 (1983-04-01), Sakurai
patent: 4489478 (1984-12-01), Sakurai
patent: 4902637 (1990-02-01), Kondou et al.
patent: 5266511 (1993-11-01), Takao
patent: 5418177 (1995-05-01), Choi
patent: 5470776 (1995-11-01), Ryou
patent: 5731217 (1998-03-01), Kadosh et al.

Affiliated with

Also associated with

Rating

Method for forming source drain junction areas self-aligned betw does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming source drain junction areas self-aligned betw, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming source drain junction areas self-aligned betw will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1214329