Non-uniform threshold voltage adjustment in flash eproms through

Details Non-uniform threshold voltage adjustment in flash eproms through Non-uniform threshold voltage adjustment in flash eproms through

1998-02-13

1999-03-30

Booth, Richard A.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438291, 438593, 438525, H01L 218247

Patent

active

058888675

ABSTRACT:
Aspects for forming a Flash EPROM cell with an adjustable threshold voltage are described. In a method aspect, the method includes forming a substrate structure to establish a foundation for cell formation, and forming a gate structure with a floating gate layer comprising polysilicon-germanium (poly-SiGe) of a non-uniform Ge concentration on the substrate structure. The method further includes forming source and drain regions within the substrate structure, the drain region having a different threshold voltage than the source region. In a further aspect, a Flash EPROM cell with an adjustable threshold voltage includes a substrate structure as a foundation for the cell. The cell further includes a gate structure on the substrate structure, the gate structure comprising a floating gate layer of polysilicon-germanium (poly-SiGe) of non-uniform Ge concentration. Additionally, source and drain regions are included in the substrate structure bordering the gate structure, the drain region having a differing threshold voltage than the source region.

REFERENCES:
patent: 4714519 (1987-12-01), Pfiester
patent: 4745079 (1988-05-01), Pfiester
patent: 5360751 (1994-11-01), Lee
patent: 5521108 (1996-05-01), Rostoker et al.
patent: 5536667 (1996-07-01), Cho
"Symmetric CMOS In Fully-Depleted Silicon-On-Insulator Using P+-Polycrystalline Si-Ge Gate Electrodes, " Neal Kistler and Jason Woo, IEDM 93, 727-730.

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