Method to fabricate capacitors in memory circuits

Details Method to fabricate capacitors in memory circuits Method to fabricate capacitors in memory circuits

1996-05-16

1999-03-30

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438396, H01L 218242

Patent

active

058888632

ABSTRACT:
A method is described for forming a dynamic random access memory cell with an increased capacitance capacitor. Semiconductor devices including a capacitor node contact region are formed. A layer of silicon nitride and an insulating layer are deposited over the devices. A contact is opened through the insulating and silicon nitride layers to the capacitor node contact region. A first layer of polysilicon is deposited over the insulating layer and within the contact opening. A layer of silicon oxide is deposited over the first polysilicon layer. The silicon oxide layer is patterned so as to leave this layer only in the area of the planned capacitor and extending outward from the contact opening a first distance. The first polysilicon layer is patterned so as to leave this layer only in the area of the planned capacitor and extending outward from the contact opening a second distance smaller than the first distance. A second layer of polysilicon is deposited over the silicon oxide layer. The second polysilicon layer is removed except for spacers on the sidewalls of the silicon oxide layer and portions underlying the spacers. The silicon oxide and insulating layers are etched away leaving the first polysilicon layer with a cylindrical shape wherein the second polysilicon layer has both a horizontal and a vertical fin on each of two sides of its structure. A capacitor dielectric layer and a third polysilicon layer are deposited and patterned to complete formation of the DRAM with capacitor.

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