Method of fabricating a MOS device with a localized punchthrough

Details Method of fabricating a MOS device with a localized punchthrough Method of fabricating a MOS device with a localized punchthrough

1997-08-05

1999-10-05

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438307, 438439, 438451, H01L 21336

Patent

active

059638117

ABSTRACT:
A method of fabricating a MOS device with a localized punchthrough stopper. In the process, a dummy layer is employed to define a well for implanting the localized punchthrough stopper. The dummy layer is preferably made of silicon nitride, which has a high etching selectivity with respect to the oxide material forming sidewall spacers of MOS devices. The localized punchthrough stopper is formed at the boundary of the lightly-doped regions and the channel by implanting impurities through the well resulting from the removal of a portion of the dummy layer adjacent to the gate structure.

REFERENCES:
patent: 5686321 (1997-11-01), Ko et al.
patent: 5893740 (1997-06-01), Chang et al.

Affiliated with

Also associated with

Rating

Method of fabricating a MOS device with a localized punchthrough does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating a MOS device with a localized punchthrough, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a MOS device with a localized punchthrough will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1182526