Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1998-02-03

2000-04-11

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Precharge

36518525, G11C 700

Patent

active

060494948

ABSTRACT:
A semiconductor memory device includes a memory cell array in which memory cell units are arranged in a matrix, each memory cell unit being constructed by connecting plural memory cells, each of which is electrically rewritable, a select gate connected to a select gate line for connecting a memory cell unit to a bitline, a precharge circuit connected to a first node of the bitline, for supplying a precharge voltage higher than an power supply voltage in programming of data, and a latch circuit connected to a second node of the bitline via a transfer gate for holding data to be programmed into a memory cell, wherein channels of the plurality of the memory cells constituting a selected memory cell unit are charged to the precharge voltage in programming of data.

REFERENCES:
Kang-Dong Suh et al, "A 3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Schame," IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995.; pp. 1149-1156.
Yoshihisa Iwata et al, "A 35ns Cycle Time 3.3V Only 32 Mb NAND Flash EEPROM," IEEE Journal of Solid-State Circuits, vol. 30 No. 11, Nov. 1995.; pp. 1157-1164.
R. Shirota et al, "A 2.3 pm.sup.2 Memory Cell Structure for 16 Mb NAND EEPROMS", IEDM '90 Technical Digest, Dec. 1990; pp. 103-106.
Tae-Sung Jung et al. "A 3.3V 128 Mb Multi-Level NAND Flash Memory for Mass Storage Applications," 1996 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 32-33.
Tomoharu Tanaka et al. "A Quick Intelligent Program Architecture for 3V-only NAND-EEPROMs" 1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 20-21.
Tomoharo Tanaka et al., "A Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3 V-Only NAND Flash Memory," IEEE Journal of Solid-State Circuits, vol.29, No. 11. Nov. 1994, pp. 1366-1373.

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