Testing hot carrier induced degradation to fall and rise time of

Details Testing hot carrier induced degradation to fall and rise time of Testing hot carrier induced degradation to fall and rise time of

1995-07-18

1996-12-24

Westin, Edward P.

Electronic digital logic circuitry

With test facilitating feature

326 83, 327288, H03K 1900, H03K 190948

Patent

active

055876650

ABSTRACT:
Performance degradation resulting from hot carrier stress is determined using a special test circuit. The test circuit is formed using a string of inverters on an integrated circuit. The string of inverters is connected in series. Every other inverter in the string of inverters uses cascaded transistors so that performance of the inverters with cascaded are not degraded by introduced hot carrier stress. For example, odd numbered inverters are each constructed using cascaded PMOSFETs and cascaded NMOSFETs and even numbered inverters are each constructed using a single PMOSFET and a single NMOSFET. On an input of the string of inverters, a first signal is placed which transitions from logic 0 to logic 1. Propagation delay of the first signal through the string of inverters is measured. Also, a second signal which transitions from logic 1 to logic 0 is placed on the input of the string of inverters. Propagation delay of the second signal through the string of inverters is measured. Then, sufficient hot carrier stress is added to the string of inverters so that inverters not constructed using cascaded transistors will have degraded performance. After introduction of the hot carrier stress, a third signal which transitions from logic 0 to logic 1 is placed on the input of the string of inverters. Propagation delay of the third signal through the string of inverters is measured. Finally, a fourth signal which transitions from logic 1 to logic 0 is placed on the input of the string of inverters. Propagation delay of the fourth signal through the string of inverters is measured.

REFERENCES:
patent: 4700089 (1987-10-01), Fujii et al.
patent: 4920287 (1990-04-01), Hartgring et al.
patent: 5245585 (1993-09-01), Voss et al.
Khandker N. Quander, Ping K. Co, and Chenming Hu, Projecting CMOS Circuit Hot-Carrier Reliability from DC Device Lifetime, IEDM 93, 1993, p. 511.
Chun Jiang and Eric Johnson, AC Hot-Carrier Degradation in a Voltage Controlled Oscillator, IRPS 1993, p. 53.

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