Method of making IGFETs in densely and sparsely populated areas

Details Method of making IGFETs in densely and sparsely populated areas Method of making IGFETs in densely and sparsely populated areas

1997-02-25

1998-08-04

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438587, 438949, 430313, 430315, H01L 2170

Patent

active

057893004

ABSTRACT:
A method of making IGFETs in densely and sparsely populated areas of a substrate is disclosed. The method includes providing a semiconductor substrate with first and second regions, forming a gate material over the first and second regions, forming a photoresist layer over the gate material, irradiating the photoresist layer with a first image pattern over the first region wherein the first image pattern has a first radiation energy per unit area of the photoresist layer, irradiating the photoresist layer with a second image pattern over the second region wherein the second image pattern has a second radiation energy per unit area of the photoresist layer, developing the photoresist layer to provide selected openings above the substrate, applying an etch using the photoresist layer as an etch mask such that the etch removes portions of the gate material over the first region with a first etch bias and removes portions of the gate material over the second region with a second etch bias to form a first gate over the first region and a second gate over the second region, wherein the first region is in an area of the substrate that is densely populated with gates, the second region is in an area of the substrate that is sparsely populated with gates, and a difference between the first and second radiation energies per unit area offsets a difference between the first and second etch biases, and forming sources and drains in the first and second regions. Preferably, the first and second image patterns are applied with different exposure times to provide different photoresist linewidths that offset the first and second etch biases for densely-packed and isolated polysilicon gates.

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U.S. Patent Application Serial No. 08/623,802, filed Mar. 29, 1996, entitled "Method of Processing a Semiconductor Wafer For Controlling Drive Current", by Fulford, Jr. et al.

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