Method of making a CMOS structure with FETS having isolated well

Details Method of making a CMOS structure with FETS having isolated well Method of making a CMOS structure with FETS having isolated well

1997-09-10

1998-08-04

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438222, 438224, 438228, 438231, H01L 218238

Patent

active

057892865

ABSTRACT:
A CMOS integrated circuit with field isolation including an NFET(s) having an isolated P-well, wherein the isolated P-well is adjusted so that it does not extend below the field isolation (e.g., STI) and the width and doping of the P-well and an underlying buried N-well is adjusted so that the depletion regions of the source/drain (S-D) diode and also the well-diode just meet (merge) without overlap in the P-well. The semiconductor device obtains bipolar effect and reduced junction capacitance in a bulk single-crystal technology. A method for fabricating the semiconductor device is also provided.

REFERENCES:
patent: 4599789 (1986-07-01), Gasner
patent: 4764480 (1988-08-01), Vora
patent: 5015594 (1991-05-01), Chu et al.
patent: 5478761 (1995-12-01), Komori et al.
patent: 5541132 (1996-07-01), Davies et al.
patent: 5698458 (1997-12-01), Hsue et al.

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