Method of forming high density buried bit line flash EEPROM memo

Details Method of forming high density buried bit line flash EEPROM memo Method of forming high density buried bit line flash EEPROM memo

1998-06-03

2000-04-11

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438221, 438222, 438259, 438262, 438270, 438296, H01L 21336

Patent

active

060487658

ABSTRACT:
A method of fabricating buried bit line flash EEROM with shallow trench floating gate for suppressing the short channel effect is disclosed. The method comprises following steps: Firstly, a pad oxide layer and a n+ (such as phosphorus) doped oxide layer is successively formed on the silicon substrate. Then, a nitride layer is deposited on all surfaces as an antireflection coating layer. After coating a patterned mask on the nitride layer to define a plurality of buried bit line regions, a dry etch is used to etch the unmask region till the silicon substrate is slightly recessed to form shallow trenches. Subsequently, the photoresist is stripped, and an oxidation process to grow an oxynitride layer on resultant surface and form buried bit line using dopants in the oxide layer as a diffusion source. After refilling a plurality of trenches with n+ doped silicon layer, a planarization process such as CMP is done to form a plain surface using the nitride layer as an etching stopped layer. A stacked ONO layer is then deposited as an interpoly dielectric layer; Finally, another n+ doped polysilicon layer is formed and patterned to be word lines.

REFERENCES:
patent: 4981812 (1991-01-01), Nishizaka
patent: 5208179 (1993-05-01), Okazawa
patent: 5340769 (1994-08-01), Miyamoto
patent: 5744847 (1998-04-01), Wen
patent: 5834358 (1998-11-01), Pan et al.
patent: 5854114 (1998-12-01), Li et al.
patent: 5872043 (1999-02-01), Chen
patent: 5880007 (1999-03-01), Varian et al.
patent: 5888881 (1999-03-01), Jeng et al.
patent: 5963818 (1999-10-01), Kao et al.
patent: 5970341 (1999-10-01), Lin et al.
Albert Bergemont et al., Low Voltage NVG.TM.: A New High Performance 3 V/5 V Flash Technology for Portable Computing and Telecommunications Applications, IEEE Transactions on Electron Devices, vol. 43, No. 9, Sep. 1996, pp. 1510-1517.
R. Kazerounian et al., Alternate Metal Virtual Ground Eprom Array Implemented in a 0.8.mu.m Process for Very High Density Applications, 1991 IEEE, pp. 311-314.
J.D. Bude et al., Secondary Electron Flash--a High Performance, Low Power Flash Technology for 0.35.mu.m and Below, 1997 IEEE, pp. 279-282.
T.P. Ong et al., CVD SiN.sub.x Anti-reflective Coating for Sub-0.5.mu.m Lithography, 1995 Symposium on VLSI Technology Digest of Technical Papers, Apr., 1995, pp. 73 and 74.
Paul-Henri Bricout et al., Short-Channel Effect Immunity and Current Capability of Sub-0.1-Micron MOSFET's Using a Recessed Channel, IEEE Transactions on Electron Devices, vol. 43, No. 8, pp. 1251-1255.
S.Y. Ueng et al., Superior Damage-Immunity of Thin Oxides Thermally Grown on Reactive-ion-Etched Silicon Surface in N.sup.2 O Ambient, IEEE Transactions on Electron Devices, vol. 41, No. 5, May 1994, pp. 850 and 851.
T. Yoshitomi et al., Silicided Silicon-Sidewall Source and Drain (S.sup.4 D) Structure for High-Performance 75-nm Gate Length pMOSFETs, 1995 Symposium on VLSI Technology Digest of Technical Papers, Apr. 1995, p. 11.

Affiliated with

Also associated with

Rating

Method of forming high density buried bit line flash EEPROM memo does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming high density buried bit line flash EEPROM memo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming high density buried bit line flash EEPROM memo will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1176050