Method of fabricating sub-quarter-micron salicide polysilicon

Details Method of fabricating sub-quarter-micron salicide polysilicon Method of fabricating sub-quarter-micron salicide polysilicon

1999-03-29

2000-08-08

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438585, 438592, H01L 21336, H01L 213205

Patent

active

061001422

ABSTRACT:
A method of fabricating a semiconductor device using a Salicide process to increase the surface area of a polysilicon gate is described. First, a polysilicon layer is formed over a substrate. A mask layer with an opening is formed on the polysilicon layer. A mask spacer is formed on the sidewalls of the opening. Part of the polysilicon layer under the opening is removed with the mask spacer and the mask layer serving as a mask. An insulating layer is formed in the opening. The mask spacer and the mask layer are removed. The polysilicon layer that is not covered by the insulating layer is removed. The insulating layer is removed to expose the surface of the remaining polysilicon layer, wherein a groove is formed on the surface of the remaining polysilicon layer. Then a Salicide process is performed to form a metal silicide layer on the substrate and the remaining polysilicon layer.

REFERENCES:
patent: 5082794 (1992-01-01), Pfiester et al.
patent: 5374575 (1994-12-01), Kim et al.
patent: 5576574 (1996-11-01), Hong
patent: 5612240 (1997-03-01), Chang
patent: 5677218 (1997-10-01), Tseng

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