Method to fabricate DRAM capacitor using damascene processes

Details Method to fabricate DRAM capacitor using damascene processes Method to fabricate DRAM capacitor using damascene processes

1999-08-17

2000-08-08

Thomas, Tom

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, 438396, 438397, 438239, 257306, 257296, H01L 218242

Patent

active

061001384

ABSTRACT:
The DRAM capacitor fabrication in terms of damascene technology is disclosed. The processes are sequentially formed with word lines, landing pads and first interpoly dielectric (IPD1) layer. Thereafter, two approaching ways can be chosen. In the first embodiment, a thin nitride barrier is formed firstly, then the bit lines and IPD2 layer are formed. After that, a line mask pattern perpendicular to the bit lines are formed to serve as mask and use the nitride caps and nitride spacers as hard masks, then etching processes are implemented to form the storage nodes touching the landing pads. For increasing the storage node areas, the line masks are then descum in order to etch the IPD2 furthermore. The etch IPD2 process is using the nitride barrier as etching stopper. Then in-situ doped poly is deposited to form the bottom electrode. In the second embodiment, most of the processes are same as the first embodiment, except the thin nitride barrier process. The latter embodiment is to form a thin nitride liner after bit lines and nitride spacers are formed.

REFERENCES:
patent: 5780339 (1998-07-01), Liu et al.
patent: 5837577 (1998-11-01), Cherng
patent: 5879986 (1999-03-01), Sung
patent: 5895239 (1999-04-01), Jeng et al.

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