Method of manufacturing a semiconductor memory device having a t

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Other Related Categories

438248, H01L 218242

Type

Patent

Status

active

Patent number

061001309

Description

ABSTRACT:
The invention provides a structure which enables a junction leak current to be reduced without reducing a capacitor area. A trench is formed in the surface of a substrate such that it is connected to a conductive region for a transistor. The structure is characterized by comprising a capacitor electrode formed on the inner peripheral surface of the trench and having its upper edge portion located below the conductive region, an insulating layer projecting inward of the trench at least from the upper edge portion of the capacitor electrode to the conductive region, thereby narrowing the diameter of the trench, a capacitor insulating film coated on the capacitor electrode, and a capacitor electrode filling the trench and contacting the capacitor insulating film.

REFERENCES:
patent: 4792834 (1988-12-01), Uchida
patent: 4794434 (1988-12-01), Pelley, III
patent: 4967248 (1990-10-01), Shimizu
patent: 5309008 (1994-05-01), Watanabe
patent: 5482883 (1996-01-01), Rajeevakumar
Toru Kaga et al; IEEE Transactions on Electron Devices, dated Aug. 8, 1988, vol. 35, No. 8, "Half-V.sub.CC Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Plate Wiring" pp. 1257-1263.

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