Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-10-22
1998-08-18
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438657, H01L 218242
Patent
active
057958041
ABSTRACT:
A method is described for making an array of dynamic random access memory (DRAM) cells having both a trench and a stacked capacitor within each cell. The method involves forming a trench in the silicon substrate at the capacitor node contact area of the DRAM cell, and depositing an N+ doped polysilicon layer to form an N+/P diode capacitor in the trench. Another N+ doped polysilicon layer is deposited and anisotropically etched back over a patterned silicon nitride/silicon oxide layer in the trench areas to form the bottom electrodes of stacked capacitors with vertically extending sidewalls. An interelectrode dielectric layer is formed on the bottom electrodes and top electrodes are formed from a patterned N+ doped polysilicon layer to complete the array DRAM trench/stacked capacitors. The trench diode capacitor electrically connected in parallel with the stacked capacitor increase the cell capacitance. The vertical extensions on the stacked capacitor further increase the capacitance of the DRAM cell.
REFERENCES:
patent: 4734384 (1988-03-01), Tsuchiya
patent: 5077232 (1991-12-01), Kim et al.
patent: 5234856 (1993-08-01), Gonzales
patent: 5362664 (1994-11-01), Jun
patent: 5521111 (1996-05-01), Sato
Chaudhari Chandra
United Microelectronics Corporation
Wright William H.
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