Static information storage and retrieval – Read/write circuit – Precharge
Patent
1996-03-13
1997-08-19
Zarabian, A.
Static information storage and retrieval
Read/write circuit
Precharge
365190, 365149, G11C 700
Patent
active
056595123
ABSTRACT:
A semiconductor integrated circuit includes a cell matrix having a large number of DRAM cells in a matrix shape; a plurality of bit line pairs which have a plurality of bit lines; a plurality of bit line differential amplifier circuits each provided in each pair of bit lines for amplifying a potential difference between the first and second bit lines; a pair of data lines for receiving a charge transmission from the bit line pairs and having a first data line connected to the first bit lines and a second data line connected to the second bit lines; a switch circuit for turning on/off the charge transmission from each bit line pair to the data line pair; a data line differential amplifier circuit for amplifying the potential difference between the first and second bit lines of the data line pair; and an amplitude limiting circuit including a transistor which has a source electrode connected to anyone of the first and second data lines, a drain electrode connected to the other of the first and second data lines, and a gate electrode having a gate potential set in the manner that the gate is conductive when the potential difference between the first and second data lines becomes a predetermined regulated value while the data line differential amplifier circuit is activated, thereby limiting an amplitude between the first and second data lines less than the predetermined regulated value by means of a conduction of the transistor.
REFERENCES:
patent: 5115412 (1992-05-01), Tobita
patent: 5124947 (1992-06-01), Nakada
patent: 5153459 (1992-10-01), Park et al.
patent: 5285416 (1994-02-01), Tokami et al.
Etoh Tsuyoshi
Koyanagi Masaru
Kabushiki Kaisha Toshiba
Zarabian A.
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