Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1994-01-31
1995-01-31
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
36518901, 365195, 395275, 395725, G11C 700, G06F 1332
Patent
active
053863852
ABSTRACT:
A synchronous memory device is provided in which a timing and control circuit (28) receives timing and control inputs. A row address buffer (38) and row decoders (40 and 42) operate to enable rows in plural memory sections (30, 32, 34, and 36). Column decoders (58, 60, 62, and 64) operate to enable columns in each of the memory sections (respectively, 32, 36, 30 and 34). The column decoders (58, 60, 62, and 64) decode addresses received from counters (respectively 52, 54, 48, and 50), an adder (46), and a latch (56). Counters (48, 50, 52, and 54) and adder (46) generate column addresses for each memory section based on a starting address, thereby allowing for internal operation at less than the external system frequency. An operation mode register (29) stores mode data for controlling certain operations, and a state machine (130) operates to prevent indeterminate operation if invalid mode data is input to the operation mode register (29).
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Donaldson Richard L.
Havill Richard B.
LaRoche Eugene R.
Nguyen Tan
Texas Instruments Inc.
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