Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-03-02
2000-01-04
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438257, 438947, H01L 21336
Patent
active
060109343
ABSTRACT:
A method of making nanometer Si islands for single electron transistors is disclosed. Initially, a pad oxide is deposited over a silicon substrate. Oxygen ions are implanted into the silicon substrate to form an oxygen amorphized region and a high-temperature annealing is performed to form a buried oxide layer in the silicon substrate. Then, a thermal silicon oxide is formed to reduce the thickness of the silicon substrate on the buried oxide layer. The thermal oxide is removed and an ultra-thin oxide layer is then formed on the silicon substrate. A plurality of silicon nitride blocks is formed on the ultra-thin silicon oxide. Afterwards, the spacers of the silicon nitride blocks are formed. The silicon nitride blocks are removed by using wet etching technique. The ultra-thin silicon oxide is etched back and the polysilicon spacers are used as hard mask to Si substrate to form a plurality of nanometer silicon islands. The ultra-thin silicon oxide is removed and an ultra-thin oxynitride layer is regrown on the nanometer silicon islands. Finally, a n+ polysilicon layer is conformally deposited onto the silicon substrate and the nanometer silicon islands.
REFERENCES:
patent: 4400865 (1983-08-01), Goth et al.
patent: 5593813 (1997-01-01), Kim
patent: 5886380 (1999-03-01), Nakajima
patent: 5923981 (1999-07-01), Qian
Guo et al., "Si Single-Electron MOS Memory With Nanoscale Floating-Gate and Narrow Channel", IEDM 96, pp. 955-956, 1996.
Anri Nakajima et al., Room Temperature Operation of Si Single-Electron Memory with Self-Aligned Floating Dot Gate, IEDM 1996, pp. 952-956.
Nobuyuki Yoshikawa et al., Single-Electron-Tunneling Effect in Nanoscale Granular Microbridges, Jpn. J. Appl. Phys. vol. 36, Pt. 1, No. 6B, Jun. 1997, pp. 4161-4165.
Murphy John
Niebling John F.
Texas Instruments - Acer Incorporated
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