Method of manufacturing a semiconductor integrated circuit devic

Details Method of manufacturing a semiconductor integrated circuit devic Method of manufacturing a semiconductor integrated circuit devic

1999-06-14

2000-09-19

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438253, 438399, 438393, 438238, H01L 218242

Patent

active

061210862

ABSTRACT:
In a DRAM, a plurality of memory cells each consisting of a memory cell selection transistor Qs and an information storage capacity element connected thereto in series are provided on a semiconductor substrate 1. An active region of the memory cell selection MISFET Qs is formed to have an isolated rectangular plan view. A part of the bit line BL extends in a direction crossing the extending direction thereof, and the extending part two-dimensionally overlaps a semiconductor region formed in the active region and is electrically connected thereto. In the DRAM having this structure, the bit line BL is formed of conductive films 16b1 and 16b2 embedded in the contact hole 14b for the bit line and in the wiring groove 15a for the bit line.

REFERENCES:
patent: Re36644 (2000-04-01), Dennison
patent: 4985718 (1991-01-01), Ishijima
patent: 5828096 (1998-10-01), Ohno et al.
patent: 5858831 (1998-10-01), Sung
patent: 5940703 (1999-08-01), Hong
patent: 5956594 (1999-09-01), Yang et al.

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