Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-04-05
2000-05-09
Thomas, Tom
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438257, 438196, 438218, H01L 21336
Patent
active
060603577
ABSTRACT:
A method for manufacturing a flash memory with a shallow trench isolation and a buried bit line. In the invention, the shallow trench isolation is used as an isolation region, so that the size of the devices can be greatly reduced and the integration of the devices can be greatly increased. Additionally, the shallow trench isolation is formed in the substrate before the buried bit line implantation step is performed, so that the short channel effect caused by the lateral diffusion of the doped ions can be eliminated. Moreover, since the neighboring doped regions are electrically coupled to each other through the polysilicon layer, the access rate of the flash memory can be enhanced.
REFERENCES:
patent: 4698900 (1987-10-01), Esquivel
patent: 5034090 (1991-07-01), Fujimura
patent: 5318921 (1994-06-01), Hsue et al.
patent: 5541130 (1996-07-01), Ogura et al.
patent: 5795801 (1998-08-01), Lee
patent: 5817567 (1998-10-01), Jang et al.
patent: 5882972 (1999-03-01), Hong et al.
patent: 5892707 (1999-02-01), Noble
patent: 5982008 (1999-11-01), Kajiyama
patent: 5994186 (1999-11-01), Bergemont
patent: 5994200 (1999-11-01), Kim
Kohyama et al., "Buried Bit-Line Cell for 64Mb DRAMs", 1990 Symposium on BLSI Technology, pp. 17-18.
Kimura et al., "Short-Channel-Effect-Suppressed Sub-0.1-um Grooved-Gate MOSFET's with W Gate", IEEE Trans. on Electron Dev., vol. 42, No. 1 Jan. 1995, pp. 94-100.
Kato et al., "A Shallow-Trench-Isolation Flash Memory Technology with a Source-Bias Programming Method", 1996 IEEE, IEDM 96-177, pp. 7.3.1-7.3.4.
Guillaumot et al., "Flash Eeprom Cells using Shallow Trench Isolation", 1996 Int'l NonVolatile Memory Technology Conf., 1996 IEEE, pp. 74-75.
Huang Jiawei
Malsawma L. H
Patents J. C.
Thomas Tom
United Semiconductor Corp.
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