Semiconductor memory device provided with an improved precharge

Static information storage and retrieval – Read/write circuit – Precharge

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36518908, 365233, 307269, 307480, 328 63, G11C 700, H03K 513

Patent

active

049186574

ABSTRACT:
For producing control signals in a semiconductor memory device, each appearing without an idling time period, a control signal generating circuit comprises a plurality of sequential logical circuits associated with the controlled circuits for supplying the control signals thereto, respectively, and the sequential logical circuits include a first sequential logical circuit responsive to an external control signal and one of the control signals fed from another sequential logic circuit for shifting a logic state thereof between a first logic level and a second logic level, but each of the sequential logic circuits except for the first sequential logic circuit are responsive to the inverse of the external control signal and the output signal fed from one of the controlled circuits for shifting a logic state thereof between the first logic level and the second logic level, so that each of the control signals are produced in the first logic level.

REFERENCES:
patent: 3801827 (1974-04-01), Sequin
patent: 4040122 (1977-08-01), Bodin
patent: 4463440 (1984-07-01), Nishiura et al.
patent: 4570082 (1986-02-01), Maley et al.
patent: 4755964 (1988-07-01), Miner

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