Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1994-12-06

1996-08-13

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

365233, 365207, G11C 700

Patent

active

055463460

ABSTRACT:
In a synchronous DRAM required to be capable of performing high-speed consecutive operations in synchronism with a clock signal, a DBI-line pair is connected between a DQ-line pair and an RDB-line pair, and pipeline operation whose single cycle time is divided into four periods is employed. This S-DRAM has following: a first precharge circuit for precharging or voltage-equalizing the DQ-line pair to a power supply voltage level in the first and forth periods only; a second precharge circuit for voltage-equalizing the DBI-line pair to a ground voltage level in the first and second periods only; a third precharge circuit for voltage-equalizing the RDB-line pair to the power supply voltage level in the first and second periods only; first and second differential amplifiers for transmitting data on the DQ lines onto the DBI lines in the third period and for holding the data on the DBI lines in the fourth period; and a third differential amplifier which transmits the data on the DBI lines onto the RDB lines in the third period and which holds the data on the RDB lines in the fourth period.

REFERENCES:
patent: 5313434 (1994-05-01), Abe
patent: 5428574 (1995-06-01), Kuo et al.
T. Takai et al., 250Mbyte/sec Synchronous DRAM Using a 3-Stage-Pipelined Architecture, 1993 Symposium on VLSI Circuits, pp. 59-60.
Y. Choi et al., 16Mbit Synchronous DRAM with 125Mbyte/sec Data Rate, 1993 Symposium on VLSI Circuits, pp. 65-66.
H. Yamauchi et al., A Circuit Technology for High-Speed Battery-Operated 16-Mb CMOS DRAM's. IEEE Journal of Solid-State Circuits, vol. 28, No. 11, pp. 1084-1091, Nov. 1993.

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