Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Patent
1998-12-29
2000-12-26
Heckler, Thomas M.
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
G06F 1342
Patent
active
061675261
ABSTRACT:
An invention for intelligently adjusting the timing of generation of a series of detection windows to maintain synchronization with the occurrence of data pulses within a stream of phase-encoded binary data is disclosed. In an embodiment of the present invention, thresholding logic is added to a limited response self-clocking decode phased locked loop to achieve a more robust data detection method and system, which is less susceptible and sensitive to noise error. In one embodiment of the system, an up/down counter is used to count to occurrence of late and early data pulses within their respective detection window, with the timing of the generated series of detection windows being adjusted when the value of this counter exceeds an upper or lower predetermined threshold value.
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Adaptec, Inc.
Heckler Thomas M.
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