4. Boots, shoes, and leggings

S. Craig Nelson

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Method and apparatus for cache memory

Boots – shoes – and leggings
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Method and apparatus for reducing instruction TLB accesses

Electrical computers and digital processing systems: memory – Address formation – Generating prefetch – look-ahead – jump – or predictive address
Reexamination Certificate

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MicroTLB and micro tag for reducing power in a processor

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
Reexamination Certificate

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Split latency decoding

Coded data generation or conversion – Digital code to digital code converters
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Profile ID: LFUS-PAI-P-1977038

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