4. Electrical transmission or interconnection systems
  5. Nonlinear reactor systems
  6. Parametrons

Robert E. Eccles

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Method and apparatus for design verification with...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Method and apparatus for reducing effect of jitter

Pulse or digital communications – Testing – Phase error or phase jitter
Reexamination Certificate

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Method and apparatus for rule file generation

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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TTL compatible merged bipolar/CMOS output buffer circuits

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent

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Profile ID: LFUS-PAI-P-1602178

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