Method and apparatus for reducing effect of jitter

Details Method and apparatus for reducing effect of jitter Method and apparatus for reducing effect of jitter

2006-09-19

2006-09-19

Fan, Chieh M. (Department: 2611)

Pulse or digital communications

Testing

Phase error or phase jitter

C375S371000, C375S375000, C375S376000, C370S516000, C370S517000, C370S518000, C348S497000, C369S044320, C369S053340, C713S400000, C713S401000, C713S500000, C713S501000, C713S503000

Reexamination Certificate

active

07110446

ABSTRACT:
Method and apparatus for reducing effect of jitter is described. More particularly, one or more taps of a delay line are selected for a reference clock signal. These selected taps each have an associated index, which is stored, and stored indices are statistically processed to select a tap of another delay line.

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