4. Static information storage and retrieval
  5. Addressing
  6. Plural blocks or banks

Richard M. Barth

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Apparatus and method for bus timing compensation

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate

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Apparatus and method for device timing compensation

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate

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Apparatus and method for pipelined memory operations

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate

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Apparatus and method for pipelined memory operations

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate

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Apparatus and method for pipelined memory operations

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate

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Profile ID: LFUS-PAI-P-142603

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