Apparatus and method for pipelined memory operations

Details Apparatus and method for pipelined memory operations Apparatus and method for pipelined memory operations

2005-11-08

2005-11-08

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S101000, C365S189080, C365S189030

Reexamination Certificate

active

06963956

ABSTRACT:
A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

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