Fixed snoop response time for source-clocked multiprocessor...

Details Fixed snoop response time for source-clocked multiprocessor... Fixed snoop response time for source-clocked multiprocessor...

2007-01-30

2007-01-30

Wiley, David (Department: 2143)

Electrical computers and digital processing systems: multicomput

Distributed data processing

Client/server

C713S401000, C713S503000, C713S600000, C710S100000, C710S120000

Reexamination Certificate

active

10042103

ABSTRACT:
An interfacing logic is implemented in one or more processors and a memory controller in a multiprocessor system. The interfacing logic enables all processors to receive snoops and snoop responses substantially at the same time by delaying data transmitted over faster busses before the data is provided to a local logic at a receiving end of the faster busses. The interfacing logic comprises two or more paths of a multiplexer component connected to a storage component. The storage components are connected to another multiplexer component for selecting one of the two or more paths. Preferably, a bus control logic in the receiving end determines how much delay is performed to compensate for delay differences between data busses.

REFERENCES:
patent: 5555382 (1996-09-01), Thaller et al.
patent: 6018620 (2000-01-01), Culley et al.
patent: 6070205 (2000-05-01), Kato et al.
patent: 6557068 (2003-04-01), Riley et al.
patent: 6754838 (2004-06-01), Burns et al.

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