Michael B. Galles

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Accumulating and distributing flow control information via...

Multiplex communications – Data flow congestion prevention or control
Reexamination Certificate

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Data synchronizer for a multiple rate clock source and...

Pulse or digital communications – Synchronizers
Reexamination Certificate

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Hierarchical fat hypercube architecture for parallel processing

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Hybrid hypercube/torus architecture

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate

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Methods and apparatus for processing packets including...

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
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Profile ID: LFUS-PAI-P-406652

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