Pulse or digital communications – Synchronizers
Reexamination Certificate
1999-09-30
2003-03-04
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
C375S355000, C375S371000
Reexamination Certificate
active
06529570
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to computer system data protection and more particularly to a data synchronizer for a multiple rate clock source and method thereof.
BACKGROUND OF THE INVENTION
For data synchronization, transmitting units in computer systems typically send out a data ready signal to the receiving unit to let the receiving unit know that data is available to be received. The receiving unit typically runs off its own core clock and thus data must be synchronized to the core clock upon receipt in the receiving unit. However, the speed of the core clock in the receiving unit may be significantly faster than the transmit clock, especially if the core clock rate is adjustable from one speed to another. A high ratio of core clock to transmit clock speed may cause an over sampling of the data ready signal resulting in the receiving unit receiving more than one sample of the data. Thus, accurate data may not be received and this problem may not be realized by the receiving unit. Therefore, it is desirable to avoid over sampling of the data ready signal in order to efficiently and accurately receive data.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated that a need has arisen to prevent over sampling of a data ready signal for data transmission in a computer system. In accordance with the present invention, a data synchronizer for a multiple rate clock source and method thereof are provided that substantially eliminate or reduce disadvantages and problems associated with conventional data synchronization techniques.
According to an embodiment of the present invention, there is provided a data synchronizer for a multiple rate clock source that includes a selector unit for receiving a data ready signal and a delayed data ready signal. The selector unit generates a select signal selected from one of the data ready signal and the delayed data ready signal in response to a speed of a core clock. A first latch unit receives the select signal and generates a latched select signal in response to the core clock. A second latch unit receives the select signal and generates a delayed select signal in response to the core clock. A signal generator generates a ready signal in response to a speed of the core clock. The signal generator selects one of the latched select signal and the delayed select signal according to the speed of the core clock.
The present invention provides various technical advantages over conventional data synchronization techniques. For example, one technical advantage is to avoid over sampling of a received data ready signal. Another technical advantage is to generate a different ready signal for a specific core clock speed. Yet another technical advantage is to shape the ready signal according to the speed of the core clock. Still another technical advantage is to integrate newer and faster computer system elements with exiting older and slower products. Other technical advantages may be readily ascertainable by those skilled in the art from the following figures, description, and claims.
REFERENCES:
patent: 5060239 (1991-10-01), Briscoe et al.
patent: 5388250 (1995-02-01), Lewis et al.
patent: 5768529 (1998-06-01), Nikel et al.
patent: 5870446 (1999-02-01), Mc Mahan et al.
patent: 6003096 (1999-12-01), Lee
Galles Michael B.
Gibbons Jon C.
Miller Steven C.
Parry David M.
Baker & Botts L.L.P.
Chin Stephen
Lugo David B.
Silicon Graphics Inc.
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