Logic level shifter for 3 volt CMOS to 5 volt CMOS or TTL

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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3072963, 307451, H03K 19017, H03K 301

Patent

active

052237516

ABSTRACT:
A logic level shifter characterized by a first inverting stage which shifts an input signal downwardly to a lower level, and a second inverting stage which shifts the lower level upwardly to an output signal level which is greater than the input signal level. Feedback from the output is used to virtually eliminate static current drain when the input logic level is 0. The method of the invention involves downwardly shifting an input range of voltages to a lower range of voltages, and then upwardly shifting the lower range of voltages to an output range of voltages which is greater than the input range of voltages. There is preferably a first inversion in the downward shift and a second inversion in the upward shift. A sensing step senses the output voltage to reduce the static current consumed by the process.

REFERENCES:
patent: 4837462 (1989-06-01), Watanabe et al.
patent: 4844563 (1989-07-01), MacMillan et al.
patent: 4926070 (1990-05-01), Tanaka et al.
patent: 4929853 (1990-05-01), Kim et al.
patent: 4965469 (1990-10-01), Kondoh et al.
patent: 5115434 (1992-05-01), Aizaki

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