Circuit to provide a time delay

Details Circuit to provide a time delay Circuit to provide a time delay

2001-10-23

2003-10-14

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S264000

Reexamination Certificate

active

06633189

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of electronic circuits and more particularly to a circuit to provide a time delay.
BACKGROUND OF THE INVENTION
A number of circuits for providing a time delay in an electrical circuit are known. These circuits suffer from significant variations in the time delay provided by the circuit. One of the reasons these circuits have significant variations is that they do not adjust for variations in the supply voltage. One solution has been to add a control stage to the delay circuit. The control stage regulates the supply current that flows between the supply terminal and the delay stage to provide a relatively constant delay time over a range of supply voltages. Unfortunately, the control circuit does not adjust for process variations in the delay cell or the control stage. Process variations occur during the manufacture of a semiconductor circuit and result in components not having exactly the electrical properties specified. Another source of variations in the delay is due to temperature changes. Temperature variations result in changes in the properties of the components making up the circuit. These changes result in variations in the delay time of the circuit.
Thus there exists a need for a circuit to provide a time delay that compensates for supply voltage variations, temperature variations and process variations to provide a substantially constant delay.
SUMMARY OF INVENTION
A circuit for providing a substantially constant delay of an electrical signal that compensates for voltage, temperature and process variations includes an inverter. A delay cell has an output that is coupled to the inverter. The delay cell includes a charge transistor coupled to a capacitor. A control circuit has an output that is coupled to a gate of the charge transistor. The output has a voltage that is proportional to a trip voltage of the inverter. The delay cell also has a discharge transistor. The control circuit contains a second output that is coupled to a gate of the discharge transistor. The second output has a voltage that is also proportional to the trip voltage of the inverter.
The circuit provides the substantially constant delay in part because of the symmetry of the circuit design. This results in symmetrical variations in all the interrelated components of the circuit. The circuit is also controlled by a mathematical formula wherein the rise time is equal to the fall time are proporational to a capacitance times a resistance.


REFERENCES:
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patent: 5748542 (1998-05-01), Zheng et al.
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patent: 6163195 (2000-12-01), Jeffersen
patent: 6191630 (2001-02-01), Ozawa et al.

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