Jeffrey S. Somers

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Adaptively generating timing signals for access to various memor

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent

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Digital data processing methods and apparatus for fault isolatio

Patent

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Fault-tolerant computer system with voter delay buffer

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate

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High performance burst read data transfer operation

Patent

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Memory controller with error logging

Excavating
Patent

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Profile ID: LFUS-PAI-P-196837

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