High performance burst read data transfer operation

Details High performance burst read data transfer operation High performance burst read data transfer operation

1991-10-04

1994-03-01

Robertson, David L.

395400, G06F 1328

Patent

active

052915808

ABSTRACT:
A memory system tightly couples to a high performance microprocessor through a synchronous bus. The logic circuits included in the memory system generate a blipper pulse signal using successive transitions of clock pulse signals other than the edges used to synchronize microprocessor and memory operations. The blipper pulse signal is logically combined with the memory's column address strobe timing signal which is derived from the synchronizing edges of clock pulse signals which defines the duration of the column address interval required for accessing of a pair of DRAM memories during successive memory cycles for providing sequences of four memory read responses with no wait state.

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patent: 4370712 (1983-01-01), Johnson et al.
patent: 5134699 (1992-07-01), Aria et al.
Goodman et al, "The Use of Static Column RAM as a Memory Hierarchy", SIGARCH Newsletter, vol. 12, Issue 3, Jun. 1984; The 11th Annual International Symposium on Computer Architecture.
"The 80486: A Hardware Perspective" by Ron Sartore, Byte Magazine, Fall 1989, pp. 67-70, 72-74.

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