Semiconductor memory device and operating method thereof

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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C365S233110, C365S189050

Reexamination Certificate

active

08000166

ABSTRACT:
A semiconductor memory device including a first clock transmission path configured to receive a source clock swinging at a CML level through a clock transmission line in response to an enable signal, and to convert the source clock into a clock swinging at a CMOS level. The device also includes a second clock transmission path configured to convert the source clock in a clock swinging at a CMOS level in response to the enable signal, and to output the converted clock through the clock transmission line and a data output unit configured to output data in response to output clocks of the first and second clock transmission lines.

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patent: 6166990 (2000-12-01), Ooishi et al.
patent: 6343036 (2002-01-01), Park et al.
patent: 6442225 (2002-08-01), Huang
patent: 6597235 (2003-07-01), Choi
patent: 6757212 (2004-06-01), Hamamoto et al.
patent: 6859079 (2005-02-01), Haraguchi et al.
patent: 2002/0141280 (2002-10-01), Hamamoto et al.
patent: 1020060130440 (2006-12-01), None
Notice of Allowance issued from Korean Intellectual Property Office on Jul. 28, 2009 with an English Translation.

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