Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2011-08-16
2011-08-16
Nguyen, Tuan T. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S233110, C365S189050
Reexamination Certificate
active
08000166
ABSTRACT:
A semiconductor memory device including a first clock transmission path configured to receive a source clock swinging at a CML level through a clock transmission line in response to an enable signal, and to convert the source clock into a clock swinging at a CMOS level. The device also includes a second clock transmission path configured to convert the source clock in a clock swinging at a CMOS level in response to the enable signal, and to output the converted clock through the clock transmission line and a data output unit configured to output data in response to output clocks of the first and second clock transmission lines.
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Notice of Allowance issued from Korean Intellectual Property Office on Jul. 28, 2009 with an English Translation.
Kim Bo-Kyeom
Kim Kyung-hoon
Yoon Sang-Sic
Hynix / Semiconductor Inc.
IP & T Group LLP
Nguyen Tuan T.
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