Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
365219, 365230, G11C 700
A pseudo static RAM having a function which enables high-speed serial read and write operations with a relatively simple circuit configuration. In the stage subsequent to an amplifier for amplifying read signals from memory cells which are output to complementary common data lines, there are provided a first flip-flop for transmitting the output signal from the amplifier to an output buffer in an ordinary read operation, a second flip-flop connected between the amplifier and the first flip-flop in a serial read operation so as to transmit the output signal from the amplifier to the output buffer in cooperation with the first flip-flop, and an address counter for successively selecting a plurality of data lines.
patent: 3787817 (1974-01-01), Goldberg
patent: 4633441 (1986-12-01), Ishimoto
Hitachi , Ltd.
Moffitt James W.
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