Control circuit for clock enable staging

Details Control circuit for clock enable staging Control circuit for clock enable staging

1999-07-09

2000-12-26

Phan, Trong

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 94, H03K 1900

Patent

active

061665649

ABSTRACT:
A control circuit for clock enable staging between first and second clock macros wherein each clock macro produces a clock signal at an output in response to a transition of a global clock signal when an enable signal has been activated. The control circuit comprises a latch element having a first input coupled to the output of the first clock macro, a second input of the latch element is coupled to the output of the second clock macro, and an output node coupled to the enable input of the second clock macro. The output node of the latch element activates the enable input of the second clock macro responsive to the clock signal at the output of the first clock macro, and inactivates the enable input of the second clock macro responsive to the clock signal at the output of the second clock macro.

REFERENCES:
patent: 5151623 (1992-09-01), Agrawal
patent: 5939898 (1999-08-01), Henkel et al.
patent: 6005416 (1999-12-01), Beakes et al.

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