Synchronous semiconductor memory device having a column disablin

Details Synchronous semiconductor memory device having a column disablin Synchronous semiconductor memory device having a column disablin

1998-03-16

2000-04-25

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 36518906, 36523003, 36523006, G11C 800

Patent

active

060552077

ABSTRACT:
Disclosed is a synchronous semiconductor memory device for prevent signals on activated and inactivated column selection lines from being overlapped, which comprises a memory cell array having at least two banks each divided into a plurality of blocks, each of the blocks having a plurality of memory cells arranged in form of matrix of a plurality of rows and columns; a timing register for generating an internal clock signal synchronized with an external clock signal; a column predecoder for decoding a column address for addressing one of the columns to generate a first address as block selection-information and a second address as column selection-information; a column decoder for selecting one of columns within block relevant to the first address in response to the second address synchronized with the Nth cycle (N is an integer) of the internal clock signal after disabling an addressed column at the (N-1)th cycle of the internal clock signal in response to a predetermined column disable signal; and a column selection line disabling circuit for generating the column disable signal only when the first address corresponding to column activated at the (N-1)th cycle of the internal clock signal is activated during the Nth cycle of the internal clock signal. With the device, even though the synchronous semiconductor memory device is operated at high speed, it is possible to prevent signals on each of the column selection lines activated and inactivated from being overlapped.

REFERENCES:
patent: 5590086 (1996-12-01), Park et al.
patent: 5742554 (1998-04-01), Fujioka
patent: 5754838 (1998-05-01), Shibata et al.

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