Method of executing read and write operations in a synchronous r

Details Method of executing read and write operations in a synchronous r Method of executing read and write operations in a synchronous r

1997-04-28

1998-05-12

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711104, 711167, G06F 1316, G06F 1200

Patent

active

057522707

ABSTRACT:
An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for external output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputers, large size calculators, work stations and personal computers can be improved.

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IBM Prepares Synch SRAM Entries, Electric News, Jun. 6, 1994, p. 70.
Child, "RISC and Pentium drive demand for SRAMs that are fastest of the fast," Computer Design Mar. 28, 1994, pp. 47-48.

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