Use of hard masks during etching of openings in integrated circu

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

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438700, 438640, 216 47, H01L 214763

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active

060543841

ABSTRACT:
With the present invention, a plurality of contiguous openings within an integrated circuit are etched with high etch selectivity. The present invention includes the step of depositing a first masking layer adjacent a first opening layer. The first masking layer has a first pattern for defining a first opening in the first opening layer. The present invention also includes the step of depositing a second opening layer adjacent the first masking layer. Additionally, the present invention includes the step of depositing a second masking layer, that is comprised of a hard mask material, adjacent the second insulating layer. The second masking layer has a second pattern for defining a second opening in the second opening layer. The second pattern is aligned with the first pattern such that the first opening and the second opening are contiguous. With the second masking layer being comprised of a hard mask material, at least one of the first opening and the second opening is readily etched with an high selectivity etch process, such as a high temperature etch and/or a high polymer etch. With high etch selectivity, the present invention is especially amenable for small-geometry integrated circuit fabrication. Moreover, the present invention may be practiced to particular advantage during a dual damascene etch for a via hole and a trench line in integrated circuit metallization.

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Wolf Stanley and Tauber Richard N. "Silicon Processing For The VLSI Era Vol. 1--Process Technology", pp. 531-534, 1986.

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