Layout method for a clock tree in a semiconductor device

Details Layout method for a clock tree in a semiconductor device Layout method for a clock tree in a semiconductor device

1998-02-13

2000-04-25

Stamber, Eric W.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

716 6, 716 18, 703 19, G06F 1750

Patent

active

06053950&

ABSTRACT:
A clock signal distribution circuit has a clock tree configuration. In the layout of the clock tree, a standard clock tree is prepared having a route buffer, a plurality of intermediate stage buffer cells and a plurality of last stage buffer cells connected in a hierarchical configuration. All of the clock lines have an equal length. If there are no set of flip-flops ina target integrated circuit corresponding to a set of last stage buffer cells, the set of last stage buffer cells are removed as a whole provided there is not other last stage buffer cells connected to a flip-flop.

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Cho et al, "A Buffer Distribution Algorithm for High-Performance Clock Net Optimization", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 84-98, Mar. 1995.
Brasen et al, "Post-Placement Buffer Reoptimization", IEEE Proceedings of Euro ASIC '92, pp. 156-161, Jun. 1992.

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