Semiconductor memory device with reduced output noise

Details Semiconductor memory device with reduced output noise Semiconductor memory device with reduced output noise

1997-01-10

1998-05-12

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Signals

3652335, G11C 700

Patent

active

057516456

ABSTRACT:
An inhibition signal CAIHT for inhibiting, in adaptation to the data output timing of an output buffer, an internal column address strobe signal int/CAS output from a CAS buffer from falling from an H level to an L level for a prescribed period is generated and then applied to the CAS buffer. During data output, the internal column address strobe signal int/CAS is inhibited from being brought into an active state for the prescribed period, so that new data can be prevented from being transferred to the output buffer during this inhibition period, whereby erroneous data resulting from output noise can be prevented from being output. Consequently, a semiconductor memory device capable of correctly outputting data without the influence of the output noise is provided.

REFERENCES:
patent: 5331593 (1994-07-01), Merritt et al.
patent: 5331601 (1994-07-01), Parris
patent: 5404335 (1995-04-01), Tobita
patent: 5488581 (1996-01-01), Nagao et al.
patent: 5532961 (1996-07-01), Mori et al.
patent: 5594704 (1997-01-01), Konishi et al.

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