High voltage CMOS circuit which protects the gate oxides from ex

Details High voltage CMOS circuit which protects the gate oxides from ex High voltage CMOS circuit which protects the gate oxides from ex

1995-09-21

1998-03-17

Westin, Edward P.

Electronic digital logic circuitry

Interface

Logic level shifting

326 81, 326121, H03K 190185

Patent

active

057291551

ABSTRACT:
In a voltage level shift circuit, a load device L11, a P-channel type MOS transistor P12 and N-channel type MOS transistors N12 and N11 are connected in series in the cited order between a high voltage source Vpp and GND. Voltages VMP and VMN having a level close to Vpp/2 are applied to the respective gates of the transistors P12 and N12 in order to suppress the level of the voltage to be applied to the gate oxide films of the MOS transistors.

REFERENCES:
patent: 4689504 (1987-08-01), Raghunathan et al.
patent: 5191233 (1993-03-01), Nakano
patent: 5243236 (1993-09-01), McDaniel
patent: 5300832 (1994-04-01), Rogers
patent: 5406141 (1995-04-01), Yero et al.
patent: 5440249 (1995-08-01), Schucker et al.
patent: 5465054 (1995-11-01), Erhart
patent: 5473268 (1995-12-01), Declercq et al.
patent: 5539334 (1996-07-01), Clapp, III et al.
Weste et al.; "Principles of CMOS VLSI Design, A Systems Perspective"; copyright 1985 by AT&T Bell Laboratories, Inc. and Kamran Eshraghian; pp. 9-10.

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