Method of forming a dual damascene trench and borderless via str

Details Method of forming a dual damascene trench and borderless via str Method of forming a dual damascene trench and borderless via str

1998-11-06

2000-12-05

Wilczewski, Mary

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438703, H01L 2132

Patent

active

061566438

ABSTRACT:
A method of forming a dual damascene structure in a semiconductor device first etches a trench pattern into a hard mask layer, followed by the etching of a via pattern in the hard mask layer. The trench is widened to completely coincide with the via pattern if the via pattern does not fall completely within the trench pattern due to alignment errors. A dielectric material is then etched in accordance with the via pattern to a predetermined depth. The dielectric material is then further etched in accordance with the via pattern and the trench pattern that has been widened to completely overlap the via. Since the via has been etched into the dielectric material with its intended size, there is no increase in via resistance and good barrier metal step coverage and substantially void-free conductor filling are provided.

REFERENCES:
patent: 5741626 (1998-04-01), Jain et al.
patent: 5795823 (1998-08-01), Avanzino et al.
patent: 5935762 (1999-08-01), Dai et al.
patent: 6001733 (1999-12-01), Huang et al.
patent: 6004883 (1999-12-01), Yu et al.

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